1. Field of the Invention
The present invention relates to a method for trimming a hard mask layer. More particularly, the present invention relates to a method for forming a gate of a MOS transistor using a tri-layer photo resist layer for improving the trimming of a hard mask layer.
2. Description of the Prior Art
With the advancing technology of the semiconductor industry, integrated circuits are being developed to increase the current computing and storage capability. As predicted by Moore's law, the number of transistors doubles every 18 months. The process of semiconductor evolves from 0.18 μm of 1999, 0.13 μm of 2001, 90 nm (0.09 μm) of 2003 to 65 nm (0.065 μm) of 2005 and is approaching 45 nm.
During the process of manufacturing metal oxide semiconductor transistors (MOS transistors), the formation of a conductive gate plays an important role. In order to meet the demand of miniaturization of the semiconductor industry, the current channel length under the gate must meet the standard of 45 nm. To meet the 45 nm channel length requirement, it is crucial to control the critical dimension (CD) during the process of exposure of the gate so as to control the line width of the conductive layer (poly-Si layer for example) after the etching process. Because the current lithographic tool techniques are incapable of obtaining the ideal CD, trimming methods are employed in some prior art methods to reduce the size of gate line width. However, most photo resist layers useful in the current gate exposure process are 193 nm photo resist layers which are intrinsically less resistant to the etching condition than 365 nm photo resist layers are on account of acrylic and cycloalkenyl polymer composition in contrast to 365 nm photo resist layers composed of aryl moiety. Furthermore, the thickness of 193 nm photo resist layers reduces as the exposure wavelength shortens. Under the dual disadvantages of poor etching resistance and less and less thickness, it is hard for 193 nm photo resist layers to meet the minimum requirement of 30 nm owing to the available thickness being 10 nm or less during the trimming process on 193 nm photo resist layers.
In order to overcome the problem, the current techniques deals with the problems by transferring the pattern on the photo resist layer to the hard mask beneath the photo resist layer. After being patterned, the hard mask is ready for the trimming process to reduce the gate line width. In addition, the hard mask must have high etching selectivity to the conductive layer used in forming gate layer. Accordingly, the trimmed hard mask is ready to be the template for etching transfer process to define the line width of gate layer.
Please refer to FIG. 1 to FIG. 3. FIG. 1 to FIG. 3 illustrate the perspective view of the process of trimming a hard mask of the prior art. Please refer to FIG. 1. There are several shallow trench isolations (STI 102) in substrate 100. A dielectric layer 104, a conductive layer 106 and a hard mask layer 108 composed of oxide materials are formed on the substrate 100 sequentially. Following that, a bottom anti-reflective coating (BARC) 110 and an imaging layer 112 are formed on hard mask layer 108 sequentially by spin coating technique. Both the bottom anti-reflective coating (BARC) 110 and imaging layer 112 together serve as a double photo resist layer 114. The reason of using double photo resist layer 114 in stead of single-layer is to increase the resolution of lithography. For the current technology, the BARC 110 is usually a 365 nm photo resist layer and the imaging layer 112 may be a 193 nm photo resist layer. In addition, the imaging layer 112 is formed by spin-coating which solves the problem of uneven thickness of the imaging layer 112. Moreover, the double photo resist layer 114 allows a thinner imaging layer 112, and a thinner imaging layer 112 may improve the focus latitude in lithography and effectively control CD. That is why the double photo resist layer 114 is so popular.
Please refer to FIG. 2. The imaging layer 112 is patterned by a photolithographic process. Then the BARC 110 is patterned by using the patterned imaging layer 112 as an etching mask. Because the imaging layer 112 is less resistant to etching than an aryl-composed 365 nm photo resist layer is due to the imaging layer 112 being a 193 nm photo resist layer which is composed of acrylic and cycloalkenyl polymers, some thickness of the imaging layer 112 is depleted when the BARC 110 is patterned. After the BARC 110 is patterned, the patterned imaging layer 112 thereon may be optionally removed. Later, an etching procedure is performed to pattern the hard mask layer 108 and to form the desired pattern of openings 200.
Please refer to FIG. 3. Now a trimming procedure is performed. The trimming procedure is a plasma etching procedure using CF4 and CHF3 as etching gases whose ratio (CF4/CHF3) is 80/15 to widen openings 200 and to narrow the width of the hard mask layer 108 for trimming.
However, because the BARC 110 is etched away faster than the hard mask layer 108 is by CF4 and CHF3, the hard mask layer 108 gets twisted, and part of the hard mask layer 108 which is close to the BARC 110 etched away more than that which is close to the conductive layer 106. Using the flawed hard mask layer 108 as an etching mask for etching conductive layer 106 is doomed to produce a flawed gate structure. Moreover, the BARC 110 is prone to line collapse during the trimming procedure and the following etching on conductive layer, which would destroy the entire process or the results.
Accordingly, it is important to develop a better method for trimming hard masks to form the gate of CMOS transistors with ideal gate length.